Thru-silicon-vias (TSV) are an important feature for stacking of chips. TSVs are formed by etching a via into a substrate, lining the via with an insulator material and a diffusion barrier layer, and then filling the remaining portion of the via with a copper material. Copper (Cu) filling, though, happens at high temperature, and upon cooling, Cu shrinks more than substrate (Si) due to its higher coefficient of thermal expansion (CTE), e.g., about 5× higher than Si.
This CTE mismatch leads to normal tension in silicon around the TSV while tangential compression in silicon due to silicon crowding around the TSV. Such tension and compression stress negatively impacts nearby device performance and reliability. The degree of such stress impact is known to have a dependence on TSV metallic liner thickness; that is, the thicker the liner, the worse the stress impact becomes. On the other hand, TSV insulation reliability is important, and a thicker metallic liner provides a better barrier function for Cu diffusion out of the TSV.